Architect FPGA – Embedded SW Architect

Job Description Summary

You will be Responsible for architecting, designing, developing, testing FPGA solutions and their integration into platforms, systems that control to run on devices with customized hardware. Typically requires a deep understanding of the characteristics of the physical device being controlled, the real-time functions it is expected to perform and the ability to design, develop, implement, and test the logic required to realize the real-time functionality. Executes standard operational/technical tasks typically subject to instructions and work routines.

As part of a multi-developer firmware team the major responsibilities will include analysis, design, implementation and testing of FPGA solutions for Square product line. The Senior Staff Designer – Electronic Hardware will report to the Senior Embedded SW Manager.#LI-ML2

Job Description

Essential Responsibilities

• Analyze complex challenging requirements to architect effective design solutions making up the overall FPGA architecture and aligns with product requirements and architecture.
• Provide forward-looking strategies for FPGA platforms and technology development, technical risks elimination and insertion, in order to make the FPGA platform reliable and the product competitive.
• Drive FPGA platform reuse strategies. Making data-driven decisions using defined trade-off criteria.
• Facilitate, drive discussions and steer cross-functional councils to solve issues, drive decisions, gain consensus, and align on technical risk mitigation strategies.
• Communicate complex messages and negotiate with others to adopt a different point of view. Influence peers to take action and negotiate with external partners and vendors.
• Utilize in-depth understanding of key technology challenges to accomplish own work and provide direction to cross-functional teams.
• Application of technical skills and analytic thinking required to solve problems, using multiple internal sources and some external sources to arrive at decisions.
• Define FPGA architecture enablers and collaborate with ART Product Owners and Product Managers on backlog definition and prioritization.
• Provide timely communications on significant issues, risks and/or developments. Maintaining a focus on safety, reliability, performance, and security for embedded systems.
• Capture and elicit detailed requirements from stakeholders to ensure comprehensive understanding and documentation.
• Handle change management and impact analysis. Assessing the effects of modifications on FPGA architecture with respect to entire system.
• Act as a resource for colleagues with less experience. Explain difficult information and work to build consensus. Use persuasion skills to influence others on topics within field.

Required Qualifications

• Bachelor’s Degree in Electrical Engineering, Computer Engineering or Computer Science
• Minimum 8 year's’ experience in FPGA design engineering
• Have legal authorization to work in Canada and be aware that any offer of employment is conditioned upon the successful completion of a pre-employment verification.

Desired Characteristics

• Working knowledge in VHDL, scripts (TCL, Bash, Python), Verilog, SystemVerilog, Xilinx/Altera/Lattice FPGA/Soc development tools and ModelSim, structure of SoC processors, memory (DDR, block RAM or distributed RAM) and FPGA cells.
• Experience with hardware debugging tools (JTAG/Logic Analyzer), prototyping and characterization of hardware (oscilloscope/laboratory), electronic circuits, ADC/DAC, Filters etc
• Familiar with standard interfaces (such as AXI/AXIS, GMII/MII, I2C, SPI, UART, USB, Ethernet etc.) , Ethernet packet structure; and Agile-SW development practices.
• Knowledge of C/C++, SystemC, OpenCL, Vivado HSL / XRT AMD framework, UVM/UVVM methodologies
• Excellent working capacity, flexible, ability to cope with periods of high workloads and solution oriented.
• Experience in all phases of the product engineering and development cycle.

Additional Information

Relocation Assistance Provided: Yes